Pooriya Navaeilavasani

Notice of the Final Oral Examination for the Degree of Master of Applied Science

Topic

Hardware Architecture for Accelerating Frequency-Domain Ultrasound Image Reconstruction

Electrical and Computer Engineering

Date & location

• Wednesday, January 10, 2024
• 12:30 P.M.
• Virtual Defence

Reviewers

Supervisory Committee

• Dr. Daler Rakhmatov, Department of Electrical and Computer Engineering, University of Victoria
  (Supervisor)
• Dr. David Capson, Department of Electrical and Computer Engineering, UVic (Member) 

External Examiner

• Dr. Daniela Constantinescu, Department of Mechanical Engineering, University of Victoria

Chair of Oral Examination

•  Dr. Abdul Roudsari, School of Health Information Science, UVic 

Abstract

Ultrasound is a widely employed biomedical imaging modality enabling non-invasive,
low-cost, and real-time diagnostics. In a typical ultrasound system, a multi-channel
transducer emits sound waves into the medium and then records returning echo signals
that are subsequently converted into an image of the subsurface structure. Coherent
plane-wave compounding (CPWC) is one of the latest ultrasound imaging techniques
that involves emitting multiple plane-wave pulses at various angles and then combining
angle-specific reconstructed image data into a final frame. This approach offers very
high data acquisition rates (e.g., hundreds or even thousands of raw data frames per
second) that are crucial for capturing fast-changing phenomena in the imaged medium.

High data acquisition rates should be matched with fast data processing to increase the
frame rate of reconstructed, or beamformed, image frames. One example of highly
efficient plane-wave beamforming methods is the Temme-Mueller algorithm that
operates in the Fourier domain. This thesis describes a novel pipelined hardware
architecture for accelerating the execution of this algorithm. The proposed design has
been coded in VDHL and implemented on a modern Xilinx field-programmable gate
array (FPGA), taking advantage of Xilinx intellectual property (IP) core reuse to reduce
development time.

Our architecture is capable of producing over 1,300 beamformed frames per second,
where each frame contains 256K complex-valued data points using the 32-bit floating
point representation for both real and imaginary parts. The correctness of our FPGA
based beamformer has been verified by comparing its output to the reference software
based implementation of the Temme-Mueller algorithm. This verification was done on
an experimental ultrasound dataset available as part of the public-domain PICMUS
evaluation framework. Our evaluation results demonstrate that the proposed design
provides a promising alternative to the conventional GPU-based approach to high-frame
rate ultrasound image reconstruction, paving the way for future algorithmic and
architectural enhancements.