Mahdi Babajan Rahaghi

Topic

High-Level Accelerator Design for Plane-Wave Ultrasound Beamforming in Fourier Domain

Department of Electrical and Computer Engineering

Date & location

• Friday, August 29, 2025

• 1:00 P.M.

• Virtual Defence

Reviewers

Supervisory Committee

• Dr. Daler Rakhmatov, Department of Electrical and Computer Engineering, University of Victoria (Supervisor)

• Dr. David Capson, Department of Electrical and Computer Engineering, UVic (Member) 

External Examiner

• Dr. Nikolai Dechev, Department of Mechanical Engineering, University of Washington 

Chair of Oral Examination

• Dr. Ralf St. Clair, Department of Curriculum and Instruction, UVic

   

Abstract

This thesis presents the design and implementation of a high-throughput receive beamforming system for Fourier-domain multi-angle plane-wave ultrasound image reconstruction using high-level synthesis (HLS) on a Xilinx Versal adaptive system on-chip device. The proposed architecture implements a customized Temme–Mueller migration algorithm entirely within the programmable logic fabric, avoiding off-chip memory and relying solely on on-chip memory and logic resources. The system operates in a stream-based multi-stage pipelined fashion, with each stage — including temporal and spatial Fast Fourier Transforms (FFTs), dynamic phase delay, spectral remapping, multi-angle coherent compounding, and inverse FFTs— realized as modular, latency-aware HLS blocks.

Unlike previous methods, the system performs remapping and interpolation without relying on large, precomputed lookup tables, instead computing all migration-related parameters on the fly. The architecture achieves a sustained processing throughput of over 500 frames per second (with five-angle compounding), enabled by four-lane parallelization and efficient pipelining across all stages. The system HLS specification is statically parameterized in terms of user-controlled FFT lengths, data frame sizes. and number of compounding angles. On the other hand, the key imaging parameters, such as speed of sound, sampling frequency, and probe geometry, are configurable at runtime. Extensive module-level simulation and architecture-level integration testing have validated the system’s correctness confirmed against a MATLAB-based reference model.