Event Details
Design Space Exploration of 2-D Processor Array Architectures for Similarity Distance Computation
Presenter: Awos Kanan
Supervisor:
Date: Thu, January 18, 2018
Time: 13:00:00 - 00:00:00
Place: EOW 430
ABSTRACT
ABSTRACT
We present a systematic methodology for exploring the design space of similarity distance computation in machine learning algorithms. Previous architectures proposed in the literature have been obtained using ad hoc techniques that do not allow for design space exploration. The size and dimensionality of the input datasets have not been taken into consideration in previous works. This may result in impractical designs that are not amenable for hardware implementation. The methodology presented in this work is used to obtain the 3-D computation domain of the similarity distance computation algorithm. A scheduling function determines whether an algorithm variable is pipelined or broadcast. Four linear scheduling functions are presented, and six possible 2-D processor array architectures are obtained and classified based on the size and dimensionality of the input datasets. The obtained designs are analyzed in terms of speed and area, and compared with previously obtained designs.
The proposed designs achieve better time and area complexities.