• home
• current students
• graduate
• events

Presenter: Mohammad Najmzadeh - Ph.D. in Electrical Engineering/Nanoelectronics, Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerla
Supervisor:

Date: Wed, July 17, 2013
Time: 14:00:00 - 15:00:00
Place: ECS 660

ABSTRACT

Abstract:

Multi-gate devices e.g. Gate-All-Around (GAA) Si nanowires and FinFETs are promising candidates for aggressive CMOS downscaling. Optimum subthreshold slope, immunity against short channel effects and optimized power consumption are the major benefits of such architectures due to higher electrostatic control of the channel. On the other hand, Si nanowires show excellent mechanical properties e.g. yield and fracture strengths of 10±2% and 30±1% in comparison to 3.7% and 4.0% for bulk Si, respectively. It would be a strong motivation to use the Si nanowires as exclusive platforms for innovative nanoelectronic applications e.g. novel strain engineering techniques for carrier transport enhancement in multi-gate 3D suspended channels or local band-gap modulation using >4 GPa uniaxial tensile stress in suspended Si channels to enhance the band-to-band tunneling current in multi-gate Tunnel-FETs. All the stress-based Si nanowire device enhancements can be done without plastic deformation and therefore, no carrier mobility degradation in deeply scaled devices.

This talk represents development of a top-down dense array of suspended Si nanowire platform on a SOI substrate to shrink the Si nanowire cross-section down to 5 nm using e-beam lithography and sacrificial local oxidation. Local oxidation was used for the first time as a local stressor and as a stress-limitation technology in this platform. To suppress the leakage current in the system, being less sensitive to the gate stack in the subthreshold regime and no need to a precise gate alignment to the suspended buckled Si nanowires, a highly doped Junctionless/Accumulation-Mode (JAM) architecture was used. An ALD high-k/metal-gate stack was used to make GAA Si nanowire architectures. Accumulation of up to ~5.6 GPa uniaxial tensile stress is reported in the buckled suspended Si nanowires while the stress level can be engineered on a single wafer by nanowire length and width modulation, local oxidation parameters and engineering the gate stack step. The Si nanowire MOSFETs were electrically characterized from 298-398 K using a Cascade Prober and a HP 4155B Semiconductor Parameter Analyzer. The buckled GAA suspended Si nanowires with cross-section down to 5 nm show ~32% electron mobility enhancement in comparison to bulk Si at the same doping level (1e18 cm-3), due to uniaxial tensile stress and at 298 K. Ionized impurity scattering was reported as the dominant scattering mechanism in the sub-5 nm cross-sectional highly doped Si nanowires in strong accumulation regime. A 3D TCAD Sentaurus device Si nanowire simulation platform was developed for corner effect analysis in the Si nanowire JAM devices as well as precise extraction of key MOSFET parameters especially for the Si nanowires with sub-5 nm cross-section. Local volume depletion/accumulation, quantum flat-band voltage and its extraction method, series resistance modulation in the JAM devices above flat-band and finally, assessment of the electron mobility extraction in the GAA Si nanowire MOSFETs in the presence of corners were reported for the first time. Micro-Raman spectroscopy was widely used to measure stress in the suspended Si nanowires on bulk and SOI substrates while the quasi-Gaussian buckling profile of the buckled Si nanowires could be used to estimate the stress level in the suspended Si nanowires in the presence of a non-transparent metal-gate thin film, assuming a uniform stress profile along the GAA Si nanowires.

Biography:

Mohammad Najmzadeh received his Ph.D. in Electrical Engineering/Nanoelectronics from Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland, in 2012. He received his M.Sc. in Microsystems with the highest possible honor, Full-GPA (5.0/5.0), from Chalmers University of Technology, Gothenburg, Sweden, in 2007 and his B.Sc. in Electrical Engineering/Electronics from Sharif University of Technology, Tehran, Iran, in 2004. He is the author of more than 20 technical/scientific articles in micro/nano-electronics covering various topics on strained multi-gate Si nanowire MOSFETs, electrical/optical characterization methods at nanoscale, modeling and simulation of nanoelectronic devices, bridge Si resonators and innovative nanofabrication methods. He is a member of IEEE and IEEE Electron Devices Society (EDS), serving as a referee for various highly impact factor journal articles in micro/nano-electronics e.g. Nanotechnology and IEEE Transactions on Electron Devices.

For further information, contact:
Reuven Gordon (250-721-5179 rgordon@uvic.ca)