Event Details
Phased Logic: A Self-Timed Digital Logic Design Style
Presenter: Dr. M.A. Thornton - Southern Methodist University
Supervisor: Dr. D. M. Miller, Professor, Department of Computer Science
Date: Fri, February 28, 2003
Time: 11:00:00 - 12:00:00
Place: Engineering Office Wing Building (EOW), Room # 430
ABSTRACT
ABSTRACT:
A self-timed digital logic design style known as Phased Logic (PL) is presented and an automated way of mapping traditional synchronous (clocked) logic to PL is discussed. Characteristics of this style of logic are explored and an optimization method known as Early Evaluation is given. Several examples of circuits realized in PL methodology are discussed.
BIOGRAPHY:
Dr. Thornton is an Associate Professor of Computer Science and Engineering at Southern Methodist University. His research interests are logic synthesis and verification.