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Presenter: Mr. Guy Lemieux - Dept. of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario
Supervisor:

Date: Fri, May 3, 2002
Time: 14:00:00 - 15:00:00
Place: EOW 430

ABSTRACT

Abstract

Programmable logic devices (PLD's) offer an alternative to rising VLSI start-up costs, but they have higher cost per chip. A major contributor to this cost is the programmable interconnect, which occupies up to 70% of the PLD area. To reduce this area, this talk will present methods of constructing and evaluating the building blocks used in PLD interconnect: sparse crossbars and switch blocks. To yield the best performance and area, the circuit design of individual routing switches is also briefly examined.

Sparse crossbars reduce N inputs down to M outputs using significantly fewer than N*M switches. A method of generating routable switch locations is built from Hall's theorem. The routability itself can be quickly tested using a network flow algorithm. Using these crossbars can reduce the number of switches by 10--85%, and routability can be improved from 1% to over 95%. Application of these structures in a PLD can realize a 10--15% area savings.

Switch blocks are used to steer signals around corners and along the length of a PLD. A mathematical framework is presented which increases routing diversity, or the number of disjoint paths in the network that reach a single destination. As well, new transistor-level switch designs will be shown to eliminate nearly all of the delay increase caused by signal fanout, resulting in smaller and faster PLDs.

For Further Information Contact
Dr. N.J. Dimopoulos (721-8902)