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Presenter: Parastoo Soleimani
Supervisor:

Date: Fri, August 18, 2023
Time: 17:30:00 - 00:00:00
Place: ZOOM - Please see below.

ABSTRACT

Meeting:  https://uvic.zoom.us/j/89007079781?pwd=M1pzS2M3a3h0L28zdUN0Z3BHZEk2Zz09 

Meeting ID: 890 0707 9781 

Password: 574992 

Note: Please log in to Zoom via SSO and your UVic Netlink ID  

Abstract:  One of the foremost challenges for using computer vision algorithms in practical applications is computational intensity which in turn may impact performance. The focus of this seminar is on improving speed performance by proposing novel algorithmic and hardware design techniques. Contributions are described for feature extraction and image matching. Further contributions of this work are related to the various steps of image matching algorithms, including scale-space generation, descriptor computation, and descriptor matching. 

Histogram of Oriented Gradients (HOG) is one of the commonly-used algorithms for feature extraction. In order to increase the speed of computation, a hardware-software co-design is presented. The proposed design of the HOG algorithm attains comparable frame rates and is shown to use fewer hardware resources in comparison with existing work in the literature.  

For scale-space generation, a real-time FPGA-based implementation of the AKAZE algorithm with non-linear scale-space generation is proposed. The proposed implementation makes two main contributions, that include (1) mapping the two passes of the AKAZE algorithm onto a hardware architecture for parallel processing of multiple image sections, and (2) designing multi-scale line buffers for reducing resource utilization. A frame rate of 304 frames per second for a 1280×768 image resolution is achieved which is shown to be faster in comparison with other published work. 

For feature description, a novel circular shifting binary descriptor is proposed which leads to an efficient rotation invariant image matching. This new method eliminates complex operations such as multiplication and division from the orientation estimation step and thus significantly lowers the number of operations for descriptor computation. For descriptor matching, a novel content-addressable memory (CAM) architecture is proposed which significantly accelerates the matching step of the image matching pipeline. The proposed method is shown to perform binary descriptor matching in only one iteration over the descriptor vectors.