Event Details
Progressive Product Reduction (PPR) Systolic Array Architecture for Polynomial GF(2^m) Multiplication and its implementation
Presenter: Ali Nia
Supervisor:
Date: Thu, April 18, 2013
Time: 14:00:00 - 00:00:00
Place: ECS 467
ABSTRACT
Abstract: Finite or Galois Fields have many important and practical applications. Galois Field can be applied to error correcting coding computer algebra systems, information theory, number theory and public key cryptosystems . The operation of multiplication in Galois Fields is quite different from the usual binary arithmetic operation and is more efficient and more widely used compared with multipliers based on normal and dual basis. Numerous hardware architecture have been proposed for polynomial basis finite field multiplication over GF(2^m) . This work is devoted to the efficient VHDL architecture design for implementation of systolic array for polynomial GF(2^m) multiplication. It concentrates on GF(2^m) multiplication and explores systolic architecture for iterative algorithms of finite field multiplication over GF(2^m) based on Irreducible trinomials using systematic linear and non linear techniques that combines affine and non linear Processing Element (PE) scheduling and assignment of computation to processors. The technique iterative multiplication algorithm using Progressive Product Reduction (PPR) will be discussed in this work.