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Presenter: Dian Ross
Supervisor: Dr. Mihai Sima

Date: Fri, November 30, 2012
Time: 13:00:00 - 00:00:00
Place: EOW 430

ABSTRACT

ABSTRACT:

Reconfigurable devices, such as Field-Programmable Gate Arrays (FPGAs), are becoming increasingly accepted for implementing digital designs due to their flexible, post-fabrication software programmability, and hardware-like performance. This flexibility both reduces the non-recurring engineering expense of designing a full-custom circuit, and eliminates the time and expense associated with custom silicon circuit fabrication; these factors combine to reduce the overall time to market when compared with an Application Specific Integrated Circuit (ASIC). Nevertheless, this flexibility comes at the cost of increased power consumption, propagation delay, and silicon are overhead.

In a bid to reduce power consumption in reconfigurable arrays for use in embedded and mobile devices, circuit architectures have been proposed that operate at sub-threshold voltages with longer propagation delay. Techniques from prior-art are analyzed across four technology nodes (180nm, 130nm, 90nm, and 65nm) in both weak and strong inversion. A new logic family, the Unfolded Multiplexor - Level Restoring Buffer (UMUX-LRB) reconfigurable interconnection is proposed for operation at both sub- and super-threshold voltages. With smaller silicon area compared with other sub-threshold circuit techniques, UMUX-LRB logic is shown to both reduce power consumption in strong inversion and improve propagation delay performance in weak inversion; the end user is able to prioritize for power or delay with the same device. Design rules and transistor sizing guidelines are presented for designing interconnection networks with reconfigurable supply voltages that can be operated across the range of sub- to super-threshold supply voltages.