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Presenter: Ali Alzahrani
Supervisor:

Date: Fri, August 17, 2018
Time: 08:30:00 - 00:00:00
Place: EOW 230

ABSTRACT

Abstract:
Embedded multi-core systems are implemented as
systems-on-chip that rely on packet store-and-forward networks-on-
chip for communications. These systems do not use buses nor
global clock. Instead routers are used to move data between
the cores and each core uses its own local clock. This implies
concurrent asynchronous computing. Implementing algorithms in
such systems is very much facilitated using dataflow concepts. In
this work we propose a methodology for implementing algorithms
on dataflow platforms. The methodology can be applied to
multi-threaded, multi-core platforms or a combination of these
platforms as well. This methodology is based on a novel dataflow
graph representation of the algorithm. We applied the proposed
methodology to obtain a novel dataflow multi-core computing
model for the secure hash algorithm-3. The resulting hardware
was implemented in FPGA to verify the performance parameters.
The proposed model of computation has advantages such as
flexible I/O timing in term of scheduling policy, execution of
tasks as soon as possible, and self timed event driven system. In
other words, I/O timing and correctness of algorithm evaluation
are dissociated in this work. The main advantage of this proposal
is ability to dynamically obfuscate algorithm evaluation to thwart
side-channel attacks without having to redesign the system. This
has important implications for cryptographic applications.