Event Details

Advanced Encryption Standard Implementation on Field Programmable Gate Arrays

Presenter: Maryam Behrouzinekoo
Supervisor: Dr. T. Aaron Gulliver

Date: Fri, November 17, 2017
Time: 12:00:00 - 13:00:00
Place: EOW 230

ABSTRACT

Cryptography provides users with secure communications and guarantees data transmission privacy and authenticity (Coron, 2006). Today the most widely used algorithm for private key encryption is the Advanced Encryption Standard (AES). It operates on 128 bit blocks of data in the form of a 4x4 matrix of bytes called the state matrix. The encryption/decryption process is performed on this matrix using key sizes of 128, 192 or 256 bits. The AES round operations include shift rows, mix columns, and sub bytes using finite field arithmetic. Numerous studies have been done on the AES cryptosystem focusing on design optimization in terms of the memory used in hardware implementation (Dyken & G.Delgado-Frias, 2009).
The sub bytes operations dominates the hardware complexity of AES due to its non-linearity. In this report, the AES hardware complexity is reduced by implementing the sub bytes operation using inversion in GF(256). This inversion is decomposed into a network of logic gates which reduces the total number of read only memory (ROM) by 88.89%, compared to using look up tables.