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Presenter: Mohammad Hossein Hajkazemi
Supervisor: Dr. Amirali Baniasadi

Date: Mon, August 12, 2013
Time: 10:00:00 - 00:00:00
Place: EOW 430

ABSTRACT

ABSTRACT:

Achieving high-performance while maintaining power within acceptable limits, continues to serve as a major challenge for IC designers. Higher performance may require more transistors, higher working frequency, lower supply voltage and smaller devices. All these trends make digital circuits more vulnerable to faults. Conventionally, there are two main approaches including modular and temporal redundancies in building fault-tolerant designs. Both approaches come with either significant power/ area overhead or huge performance penalty. While in this presentation we discuss these issues, we introduce an alternative Fault-Tolerant Power-Aware Hybrid Adder for high-performance processors. Unlike previous studies, FARHAD uses an aggressive adder to produce the initial outcome and a low-power adder to generate the second outcome. It achieves the high energy-efficiency of time-redundant solutions and the high performance of resource-redundant adders.