Event Details
On Kalman Filter Implementation on FPGAs
Presenter: Zorawar Bhatia
Supervisor: Dr. Mihai Sima
Date: Wed, December 12, 2012
Time: 13:00:00 - 00:00:00
Place: EOW 430
ABSTRACT
ABSTRACT:
The following presentation attempts to highlight and address the implementation and performance of a Kalman filter on an FPGA. The reasons for choosing the Kalman filter and the platform for implementation are highlighted as well as an in depth explanation of the components and theory behind both are given.
A controller system which allows a good performance of the Kalman filter on it is developed in VHDL. The design of the controller is dictated by the analysis of the Kalman filter which ensures only the most necessary components and operations are built into the instruction set. The controller is made up of several components including the loader, the ALU, Data RAM, KF IO, Control Store and the Branch Unit. The components working in conjunction allow the system to interface though a handshaking protocol with a peripheral of arbitrary latency. The control store is loaded with program code that is determined by converting human readable assembler into machine code through a Perl encoder. The controller system is tested and verified though an extensive testbench environment that emulates all outside signals and views internal operations. The controller system is capable of five matrix operations which are computed in parallel due to the FPGA development environment, which is far superior in this case to an all software solution, due to the vector operations inherent in the Kalman filter algorithm.