Event Details
Implementation of Binary and Ternary Convolutional Codes on an FPGA
Presenter: Bharath Madela
Supervisor:
Date: Wed, September 1, 2021
Time: 11:00:00 - 12:00:00
Place: via Zoom - please see link below
ABSTRACT
Zoom Meeting Link: https://uvic.zoom.us/j/81772566339?pwd=Vkt5eHZ0bE9VQnY0c0tEeUFvd0NVdz09
Meeting ID: 817 7256 6339
Password: 053662
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Abstract:
In modern wireless communication systems, the channels are corrupted by noise and interference. To address this issue, error control coding is employed to reliably transfer data. Convolutional codes are widely employed as they are easy to encode and decode. The focus of this work is the implementation of binary and ternary convolutional codes on an FPGA. As most data is binary, binary to ternary conversion is employed to implement ternary convolutional codes on an FPGA which is a binary device. The design architecture for both types of codes is discussed and comparisons are made based on structure, data rate, speed and resource utilization.